The frequency of clock signals used in typical high performance CPU's has been steadily increasing, causing an increase in the complexity of CPU's due in part to physical packaging techniques used to accommodate high frequency clock circuits including high frequency clock input/output (I/O) circuits. In direct conflict with the trend towards higher frequency clock signals, is the need, caused by economic pressures in the industry, to provide simpler designs for CPU packages.
To avoid the need for high frequency I/O clock signals in CPU packages, some high performance CPU's use on-chip clock synthesis, based on phase locked loop (PLL) technology, to generate the desired high frequency clock signals. In these CPU's, a lower frequency reference clock signal is provided to the CPU, and the PLL within the CPU generates a high frequency clock signal having a predetermined frequency and phase relationship with the reference clock signal. This scheme avoids the need for high frequency clock I/O signals.
In multiprocessor systems, and in systems that provide high speed interfaces to memory devices and other chips, there are typically stringent phase and frequency requirements for high speed clock signals generated within a CPU. Because of these stringent requirements, global clock buffers and clock frequency dividers in the CPU are typically contained within a phase locked loop in a CPU, rather than contained outside the loop where frequency divider value changes could be handled in a simpler manner. The inclusion of the frequency dividers and clock buffers within the phase locked loop can introduce transient errors in the output clock signal when the frequency divider values are changed.
It is desirable in computer systems to provide real time automatic management of power consumption. One of the ways in which computer systems manage power consumption is to control the frequency of CPU on-chip generated clock signals. Typically, in a standby, low power consumption mode of a computer system, clock frequencies are lowered by a factor of two, resulting in a reduction of power consumption by the CPU of approximately one-half. Clock frequencies are typically lowered using software controlled frequency dividers contained within the phase locked loop clock synthesis circuit of the CPU. These frequency dividers reduce an input clock signal by a divider value controlled by software.
As discussed above, the frequency dividers are contained within the phase locked loop to allow the CPU to meet stringent phase and frequency requirements imposed on the clock signals. As a result, when the values of the frequency dividers are changed, transients may be introduced into the phase locked loop, causing the relative phase and frequency of the clock signal generated by the PLL to vary. This variation can prevent proper operation of the CPU and/or cause failure of devices coupled to the CPU due to timing errors relative to the reference clock signal.
It is an object of the present invention to provide a reduction of the transient signals discussed above.